The integrated circuit industry continues to progress in electronic circuit densification and miniaturization. This progress has resulted in increasingly compact and efficient semiconductor devices, which in turn enable the systems into which these devices are incorporated to be made smaller and less power consumptive.
Integrated circuits are fabricated with devices that have microscopic features that can only be manufactured with processing steps that require careful equipment alignment and timing. The manufacturing costs of integrated circuits are expensive because: (1) the processing steps must be accomplished with costly and sophisticated equipment and experienced operators; and (2) such steps are not always successful. For example, if the processing equipment, such as a mask, is inadvertently misaligned, then the integrated circuit may be fabricated incorrectly and fail. As a result, processing yields decrease and production costs increase. Therefore, to reduce manufacturing costs, a fabrication process that has enhanced process margins is desirable. Such a process would permit successful fabrication of integrated circuits, despite minor misalignments.
A typical integrated circuit includes a semiconductive substrate, upon which active and passive devices are formed. These devices are encapsulated in insulating material, and patterned conductive layers are formed over the insulating material to carry signals to the devices. Conductive contacts are used to electrically connect the devices with the overlying conductive layers. These contacts extend vertically downward through the insulating material to connect the conductive layers with doped regions on the substrate or with portions of the devices. Accordingly, these contacts are often referred to as “contacts to silicon” or “contacts to substrate.” The patterned conductive layers, in turn, can be connected to other conductive layers through vias or other conductive structures.
During fabrication, the active and passive devices are first formed on the semiconductor substrate, and are encapsulated by the insulating material. Openings are then formed in the insulating material, and conductive contact material (e.g., tungsten or doped polysilicon) is deposited in these openings to form the contacts. An etching procedure is then commonly performed to remove unwanted contact material from the top surface of the insulating material.
A conductive layer of a different material (e.g., aluminum) is then formed over the insulating material and contacts. The conductive layer is then patterned and etched, using an etching process that selectively etches the material of the conductive layer. The result is a conductive layer with traces overlying and connecting with the top surfaces of the contacts.
Portions of the conductive layers or structures (e.g., contacts) that are supposed to be electrically connected are referred to as “related metals.” This is distinguishable from “unrelated metals,” which refers to portions of the conductive layers or structures that are supposed to be electrically isolated from each other. Unrelated metals typically carry independent signals.
Because the contacts and conductive traces are formed during different processing steps, it is necessary to tightly control the photolithography and etching processes so that each contact sufficiently connects with its corresponding, related metal portion within the patterned conductive layer. For example, the photomask used during the photolithography process must be precisely aligned, the timing of the duration of the etching process must be accurate, and the steppers must be tightly controlled. If these or other sub-processes are not sufficiently accurate, then one or more contacts may provide a short between unrelated metals within the overlying conductive layer, causing device failure or performance degradation.
FIG. 1 illustrates a side, cross-sectional view of a portion of a semiconductor wafer after a successful etch of an overlying conductive layer, where a contact 102 accurately connects with a related, first metal portion 104 of the conductive layer. The conductive layer includes first metal portion 104 and second metal portion 106. Metal portions 104 and 106 are adjacent to each other within the same patterned layer, and are electrically isolated from each other by insulating material 108. For the purposes of this description, metal portions 104 and 106 are unrelated metals.
When accurately aligned, the top surface of contact 102 is connected with the first metal portion 104. The contact 102 also is formed in an insulating material 110, and thus is electrically isolated from the second metal portion 106. The likelihood that contact 102 will short to the second metal portion 106 is dependent on the distance 112 through the insulating material 110 between the contact 102 and the second metal portion 106. Because the distance 112 between the contact 102 and the second metal portion 106 is relatively long in terms of the processing technology de jure, in the example illustrated in FIG. 1, a low likelihood exists that a short will develop across contact 102 to unrelated metal portion 106.
FIG. 2 illustrates a side, cross-sectional view of a portion of a semiconductor wafer after unsuccessful processing of an overlying conductive layer, where first metal portion 204 of the conductive layer is inaccurately aligned with a related contact 202. As with the example illustrated in FIG. 1, first metal portion 204 and second metal portion 206 are unrelated metals. Because the distance 212 between the contact 202 and second metal portion 206 is relatively short, a much higher likelihood exists that a short will develop across contact 202 to the unrelated metal 206. This may result in device failure or possibly impact device performance negatively.
As device sizes continue to decrease, the margin of error in alignment and etching process timing also decreases, making it more difficult to accurately align the metal portions in the overlying conductive layers with their corresponding contacts. As explained above, the photolithography and etching processes for patterning the conductive layers must be tightly controlled, and as immune as possible to process variations that may negatively affect the accuracy of these processes. For example, in a robust process having sufficient process margin, the accuracy of the photolithography and etching processes should not be affected by normal process variations. Such variations could include, for example, ambient conditions, vibration, which particular stepper or etcher is used, whether or not the fabrication chamber had been cleaned or otherwise disturbed, who the operator was who entered the processing parameters into the computer, or other process noise that inherently occurs minute-to-minute, day-to-day.
Accordingly, what are needed are processes that are more robust, which will result in higher manufacturing yields and will enable device sizes to continue to be decreased. In particular, what are needed are processes that are more tolerant of misalignments that might occur while masking and etching an integrated circuit's conductive layers, thus reducing the incidence of shorting between these unrelated metal portions. Also needed is an interconnect structure (e.g., a contact) that accurately self-aligns with its corresponding, related metal portion.